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Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
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| Zeitschriftentitel: | ACM Transactions on Design Automation of Electronic Systems |
|---|---|
| Personen und Körperschaften: | , |
| In: | ACM Transactions on Design Automation of Electronic Systems, 16, 2011, 4, S. 1-29 |
| Format: | E-Article |
| Sprache: | Englisch |
| veröffentlicht: |
Association for Computing Machinery (ACM)
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| Schlagwörter: |
| author_facet |
Wang, Xiaofang Gupta, Pallav Wang, Xiaofang Gupta, Pallav |
|---|---|
| author |
Wang, Xiaofang Gupta, Pallav |
| spellingShingle |
Wang, Xiaofang Gupta, Pallav ACM Transactions on Design Automation of Electronic Systems Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Computer Science Applications |
| author_sort |
wang, xiaofang |
| spelling |
Wang, Xiaofang Gupta, Pallav 1084-4309 1557-7309 Association for Computing Machinery (ACM) Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Computer Science Applications http://dx.doi.org/10.1145/2003695.2003701 <jats:p>Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges. Multiprocessor-on-programmable-chip, which integrates software programmability and hardware reconfiguration, provides substantial flexibility that results in shorter design cycles, higher performance, and lower cost. In this article, we present an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations. Given an application with specific energy-performance and resource constraints, our methodology aims to customize the architecture to match the diverse computation and communication requirements of the application tasks. Graph-based analysis of the application drives system synthesis that employs a precharacterized, parameterized hardware component library of functional units. Extensive experimental results for three diverse applications are presented to demonstrate the efficacy of our design methodology.</jats:p> Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs ACM Transactions on Design Automation of Electronic Systems |
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| title |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_unstemmed |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_full |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_fullStr |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_full_unstemmed |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_short |
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_sort |
resource-constrained multiprocessor synthesis for floating-point applications on fpgas |
| topic |
Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Computer Science Applications |
| url |
http://dx.doi.org/10.1145/2003695.2003701 |
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2011 |
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1-29 |
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<jats:p>Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges. Multiprocessor-on-programmable-chip, which integrates software programmability and hardware reconfiguration, provides substantial flexibility that results in shorter design cycles, higher performance, and lower cost. In this article, we present an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations. Given an application with specific energy-performance and resource constraints, our methodology aims to customize the architecture to match the diverse computation and communication requirements of the application tasks. Graph-based analysis of the application drives system synthesis that employs a precharacterized, parameterized hardware component library of functional units. Extensive experimental results for three diverse applications are presented to demonstrate the efficacy of our design methodology.</jats:p> |
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| description | <jats:p>Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges. Multiprocessor-on-programmable-chip, which integrates software programmability and hardware reconfiguration, provides substantial flexibility that results in shorter design cycles, higher performance, and lower cost. In this article, we present an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations. Given an application with specific energy-performance and resource constraints, our methodology aims to customize the architecture to match the diverse computation and communication requirements of the application tasks. Graph-based analysis of the application drives system synthesis that employs a precharacterized, parameterized hardware component library of functional units. Extensive experimental results for three diverse applications are presented to demonstrate the efficacy of our design methodology.</jats:p> |
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| spelling | Wang, Xiaofang Gupta, Pallav 1084-4309 1557-7309 Association for Computing Machinery (ACM) Electrical and Electronic Engineering Computer Graphics and Computer-Aided Design Computer Science Applications http://dx.doi.org/10.1145/2003695.2003701 <jats:p>Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges. Multiprocessor-on-programmable-chip, which integrates software programmability and hardware reconfiguration, provides substantial flexibility that results in shorter design cycles, higher performance, and lower cost. In this article, we present an application-specific design methodology for multiprocessor-on-programmable-chip architectures that target applications involving large matrices and floating-point operations. Given an application with specific energy-performance and resource constraints, our methodology aims to customize the architecture to match the diverse computation and communication requirements of the application tasks. Graph-based analysis of the application drives system synthesis that employs a precharacterized, parameterized hardware component library of functional units. Extensive experimental results for three diverse applications are presented to demonstrate the efficacy of our design methodology.</jats:p> Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs ACM Transactions on Design Automation of Electronic Systems |
| spellingShingle | Wang, Xiaofang, Gupta, Pallav, ACM Transactions on Design Automation of Electronic Systems, Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs, Electrical and Electronic Engineering, Computer Graphics and Computer-Aided Design, Computer Science Applications |
| title | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_full | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_fullStr | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_full_unstemmed | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_short | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| title_sort | resource-constrained multiprocessor synthesis for floating-point applications on fpgas |
| title_unstemmed | Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs |
| topic | Electrical and Electronic Engineering, Computer Graphics and Computer-Aided Design, Computer Science Applications |
| url | http://dx.doi.org/10.1145/2003695.2003701 |